A NAND flash memory includes a cell array. The cell array includes an array of NAND cell units. Each NAND cell unit includes a plurality of memory cells connected in series. The ends of each NAND cell unit are connected to a bit-line and a source-line via select gate transistors, respectively.
In each NAND cell unit, the control gates of the memory cells are connected to different word-lines. In the NAND flash memory, a plurality of memory cells are connected in series and share sources and drains. The memory cells also share select gate transistors and their bit-line contacts and source-line contacts. The unit memory cell can thus have a smaller size. The word-line and the memory cell's element region each have a shape close to a simple stripe pattern. The NAND flash memory can thus easily be made more compact. Therefore, the NAND flash memory provides a large capacity flash memory.
As the memory cells become smaller, the number of memory cells included in one memory cell array increases. In proportion to this, the circuit area of the sense amplifier unit also increases, for example. The increase of the circuit area of the peripheral circuits results in the increase of the length of the bus wiring in the sense amplifier unit. Repeatedly passing a current through the bus wiring of a longer length results in the increase of the power consumption.